CAD STA - Herzliya

Summary

We are looking for talented engineers to join our CAD STA team, in this role you will be responsible for all aspects of timing including working with designers for timing changes, helping construct/modify flows, timing analysis and timing closure, facilitate and drive STA methodology changes, optimize ECO process and interacting closely and collaborating with the global CAD organization and the PD various teams. Relevant PD or STA experience is a big plus

Key Qualifications

Familiar with all aspects of STA of large high-performance SoC or Processor designs in deep sub-micron technologies

Proficiency in analysis, tools, and methodologies for timing closure

Good understanding of noise, cross-talk, OCV effects, margins, and constraints

Good communicator who can accurately assess, describe issues to management and follow solutions through to completion

Familiarity with timing and power ECO techniques and implementation is a plus

Description

- Working with design teams to understand and debug issues related to constraints, flow scripts, and timing closure

- Facilitate and drive STA methodology changes to improve overall STA flows

- Create/maintain scripts and methods for timing analysis and power reduction

- Deep analysis of timing paths to identify key issues

- Implement infrastructure/scripts to facilitate large scale timing reports mining and visualization

- Working with Physical Design team, highlighting issues and best practices

Education & Experience

Bsc in EE/ CE

Role Number: 200393703