Summary

In this role you will be familiar with cutting edge power management techniques including power management ICs control schemes, Chip power state transitions, SoC boot process and HW security solutions. You will define uArch spec, implement HW including RTL and UPF coding, synthesize the digital design to the latest process nodes and participate in the implementation process.

Your responsibilities in this role likely to include:

Micro-architecture definitions at the unit level

RTL coding, block level simulations and synthesis

Work closely with verification team on block/top level to ensure timely delivery of quality designs

Work closely with physical design team to optimize the design and to meet the targets set for a certain unit (area, timing, and power)

Key Qualifications

5+ years experience in SoC pre or post silicon development (Silicon validation, Dynamic verification, platform architecture or similar)

Familiar with the various backend tools (synthesis and STA).

Familiar with advanced design practices (Clock/Voltage domain crossing, DFT and Low Power Design).

Familiar with verification methodologies.

Strong Verilog/System Verilog skills.

Experience with scripting and programming experience using several of the following: Perl, C, C++, and TCL.

Description

Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products very quickly.

Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple.Do you want to join us to help deliver the next groundbreaking Apple products?

The Apple SoC design team is looking for an experienced engineer to develop Apple's compute SoCs power management system. Role expectations include working with partner Design teams, Physical design, verification, Platform Architecture and Software teams to define the power system micro architecture, implement the required HW and integrate it to a complex multi chip system.

Education & Experience

BS/MS in EE/CE

Role Number: 200212676