NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s motivated by great technology—and outstanding people. We are leading the way in groundbreaking developments in Artificial Intelligence, High-Performance Computing and Visualization. The GPU, our invention, serves as the visual cortex of modern computers and is at the heart of our products and services. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world!

We are seeking Distinguished CPU Performance Architects to build next generation CPU cores in support of a diverse array of NVIDIA products. If you are passionate about improving CPU performance through innovative CPU microarchitectural ideas, modeling them to demonstrate merit and then seeing them through implementation and Silicon bring-up; read on!

What You'll Be Doing

• Collaborate with other micro-architects and senior designers to propose and demonstrate the merit and limitations of innovative core CPU & Fabric microarchitectural features to drive up performance per area per power on various targeted workloads.
• Do the detailed performance modeling and debug, and studies to support inclusion of these features in the next generation core microarchitecture on the basis of performance, area or power improvement
• Partner with design and verification leads to iterate through specification, implementation in RTL and verification of the microarchitecture features to achieve target functionality, performance, frequency, area, power and verifiability
• Collaborate with Silicon Bring-up and Product teams to verify and debug the microarchitecture and its delivered performance
  
  

• M.Sc. or PhD in a relevant CPU and Fabric microarchitecture area or equivalent experience
• At least 12+ years of experience
• Prior experience innovating and architecting around Fabric Congestion Management & QoS features such as cache capacity and memory bandwidth apportioning mechanisms in large core-count systems is required.
• Prior experience in CPU, Fabric & SOC memory subsystem (caches, prefetchers etc.) large core-count SoCs and core CPU microarchitecture is required.
• A deep understanding of the state of the art of CPU microarchitecture and architecture with experience in one or more of the following broad areas:
• Memory Subsystem CPU micro-arch (MMU/TLB, Address Gen, Load/Store Units, L1, L2 caches, Prefetch)
• System / SOC Fabric & Memory Subsystem Uarch
• Large System Cache Coherency experience
• Experience in control theory design and mechanisms for dynamic feedback systems is highly desirable.
  
  

• A technology enthusiast and passionate about what you do
• Strong collaborative and interpersonal skills, and a proven ability to effectively guide and influence the merits and drawbacks of the microarchitectural ideas to fellow micro architects, and implementation leads in a variety of media, both verbally and through presentations and documents.