NVIDIA's Backend team is looking for hardworking and self-motivated candidates to take part in planning and crafting our next-generation designs. Our designs help empower the world's leading high-performance computing and AI computing. We are dynamic, upbeat, and constantly challenge the status quo. We work and interact closely with post-silicon and FE teams to deliver the best, state of the art products.

What You'll Be Doing

• Build a Full-Chip floor plan layout design from early assembly/planning through implementation and signoff.
• Work closely with partition owners and Full Chip STA engineers to assure high quality and timely convergence.
• Involved in defining and implementing efficient and high-quality Full Chip physical design tools, flows, and methodologies.
• As a part of your role, you will gain hands-on experience in implementing unit/partition level BE design (RTL2GDS).
  
  

• B.S. in Electrical Engineering or Electrical Practical Engineer certificate, or equivalent experience.
• At least 5 years of relevant experience.
• Proven experience in P&R and Layout tools, TCL scripting, expertise in Netlist-to-GDSII flow is an advantage.
• Great teammate, responsible and motivated.
• Experience in unit and top-level floor planning, full-chip clock tree, power grid planning, 7nm DRC/LVS.