Senior Chip Design Engineer

Description

Annapurna Labs, as part of AWS, is looking for talented engineers to help us develop the semiconductor platform, which is based on a revolutionary architecture.

Take part in the development of cutting-edge products within disruptive system architecture. You will have the opportunity to work on the technologies that power the world’s largest Cloud provider, within a dynamic, open, and fast-paced environment. Amazon Web Services provides a highly reliable, scalable, low-cost infrastructure platform in the cloud that powers hundreds of thousands of businesses in 190 countries around the world.

Looking for exceptional Senior engineers to join the top-tier team that develops next generation semiconductor platform based on revolutionary architecture. Engineers will participate in design and verification activities working on our next generation products.

You’re invited to take part in developing, integrating and deploying cutting-edge technologies. Starting from identification and definition of project requirements, architecture, feature development and collaboration with the different groups.

Your design will be integrated as part of the nitro SOC on millions of servers worldwide - it is an opportunity to have an impact at such a large scale.

As a Senior Chip Design engineer and a member of the Nitro project, you will have an impact over the device through its entire lifecycle, from product definition stage to mass production. You will work in close collaboration with multiple groups including Architecture, Software, Verification, Backend, DFT and more.

About

If you are interested in hearing more about Annapurna and the Nitro project, you are welcome to watch the following videos:

AWS re:Invent 2022 - Silicon innovation at AWS:

https://www.youtube.com/watch?v=O6EMdeuq_s8

Nitro System Architecture: https://www.youtube.com/watch?v=02EbskIXCOc

Deep dive on the AWS Nitro System: https://www.youtube.com/watch?v=jAaqfeyvvSE

We are open to hiring candidates to work out of one of the following locations:

Tel Aviv, ISR

Basic Qualifications

• 6+ years of experience in chip design.
• Verilog / System Verilog
• Fluent with Scripting (C* / Perl / Python/ TCL)
• BSc degree in Computer Engineering/BS Computer science/Electrical Engineering.
• Very good communication skills
  
  

• Experience with full SOC cycle – Synthesis / STA / CDC / Lint.
• Experience with Design Automation.
• Protocols: PCIE, DDR, CHI, AMBA.
• Architecture of NOC, Coherent and non-Coherent fabrics.
• Higher degree in technical related field is an advantage.