Full Chip Layout Lead

Which department will you join?

Mobileye EyeC VLSI team - a group designing the chips for RADAR and LiDAR systems for ADAS and autonomous cars. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering.

We’re looking for a Full Chip Layout Lead to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.

What will your job look like:

• Leading Full Chip Layout activities & methodologies for a brand new SoC, from definition to Tape Out.
• Floor Planning Top to Bottom & Bottom up - FC, Sub System & Block level.
• IO Pad, Bump, RDL & ESD planning & implementation, co-designing with Package & Board.
• Involved in chip architecture, in close collaboration with the design & architecture teams.
• Exploring different floorplan structures to achieve both best area & ease of convergence.
• Physical verification owner, defining Physical Verification methodologies & activities for Full Chip, Sub System & Block Level.
• Working with engineers to identify and overcome roadblocks and obstacles.
  
  

• BSc/MSc in Electrical Engineering/Computer Science.
• 8 years of experience in VLSI backend (RTL2GDS).
• 5 years of experience in Full Chip Integration & verification on complex SoCs.
• Expert knowledge in floor planning, integration & signoff methodologies for hierarchical designs.
• Physical Verification Expert (DRC/LVS/PERC).
• Experience with IO Pad, Bump & ESD planning.
• Experience in technically leading complex backend activities, preferably of complete SoC's.
• Expert knowledge of the entire backend design flow from RTL to TO. (Synthesis, FP, PnR , CTS , STA, EM/IR, Chip Integration & Physical Signoff).