SoC Physical Technical Expert

Which department will you join?

Our VLSI Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility. Each Physical Design engineer has an end-to-end responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve converges. We do not consist of a CAD team & each engineer may have vertical & horizontal domain ownership allowing personal development and a meaningful contribution & impact on the entire team. Our SoC products are new & 1st generation of their kind, co-designed along with package & board teams. Full Chip, subsystems & blocks floorplan & RTL design are brand new, providing new challenges & interesting work environment.

What will your job look like:

• Work with engineers to identify and overcome roadblocks and obstacles
• Work in close collaboration with the front-end team
• Floorplan exploration and closure
• STA Drive closure together with the STA owner
• Drive PnR closure on both cluster and full-chip level
• Work in close collaboration with DFT and UPF teams
  
  

• BSc/MSc in Electrical/Computer engineering
• Layout signoff expert
• 7 years of experience in VLSI backend (RTL2GDS)
• Expert knowledge of the entire backend design flow (floorplanning, STA, CTS, PnR, IR, EM, Physical verification, chip integration, high-frequency designs)
• Deeply familiar with Physical Design EDA tools for both implementation and signoff (such as Synopsys, Cadence, etc.)