SoC Physical Design Technical Expert

Which department will you join?

Mobileye EyeC VLSI team - a group designing the chips for RADAR and LiDAR systems for ADAS and autonomous cars. The group is responsible for all disciplines of VLSI development, including but not limited to Logic Design, Design Verification, Microarchitecture, Analog and circuit design and layout, Physical and structural design (backend), Product and test engineering. We’re looking for a SoC Physical Design Technical Expert to join the growing Physical Design Team, responsible for state of the art SoC design from definition to Tape-Out.

What will your job look like:

• Work with engineers to identify and overcome roadblocks and obstacles
• Work in close collaboration with the front-end team
• Floorplan exploration and closure
• STA Drive closure together with the STA owner
• Drive PnR closure on both cluster and full-chip level
• Work in close collaboration with DFT and UPF teams
  
  

• BSc/MSc in Electrical/Computer engineering
• Layout signoff expert
• 8+ years of experience in VLSI backend (RTL2GDS)
• Expert knowledge of the entire backend design flow (floorplanning, STA, CTS, PnR, IR, EM, Physical verification, chip integration, high-frequency designs)
• Deeply familiar with Physical Design EDA tools for both implementation and signoff (such as Synopsys, Cadence, etc.)