Verification Engineer

For a hi-tech company developing hardware components for communication devices, with offices in the center
The Verification Engineer will be responsible for different HW blocks at module-level and sub-system level and is expected to:
" Have an expert-level understanding of assigned HW blocks as well as a good understanding of the block in the context of whole system.
" Communicate with architect, designer, algorithm and other verification engineers to lead complex verification tasks, both on module-level and sub-system testing.
" Design complete verification environments.
" Implement DV in full UVM environment.
דרישות התפקיד
" Engineering degree with 6+ years of hands-on experience in ASIC verification using UVM System Verilog
" Experience in unit-level as well as subsystem/full-chip verification.
" Experience working on complex ASIC or SOC designs
" ?Experience with Formal Verification - an advantage
" Good knowledge of C/C++ is a plus
" System-Level understanding
" Experience with SOCs in the communications field - an advantage