Senior Physical Design Full Chip STA Engineer

NVIDIA is looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.

What you'll be doing:

Perform advanced Static Timing Analysis (STA) for NiC and SoC projects.

Running Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.

Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages.

Responsible for a full timing closer and quality approval from pre-layout STA model through signoff.

What we need to see:

B.SC./ M.SC. in Electrical Engineering.

At least 6+ years of hands-on STA experience.

Experience in Prime Time and signoff methodologies.

Excellent leadership capabilities.

Ways to stand out from the crowd:

Knowledge in physical design flows and methodologies (Synthesis, PNR, DFT designs).

Trong background of Prime time tool.

Great teammate.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking individuals in the world working for us. If you're creative and autonomous, we want to hear from you! NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.