At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an exceptionally talented IP PD lead. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day.. This role is for a IP PD lead who will enable us to produce fully functional first silicon IP designs. The responsibilities include all phases of pre-silicon development from definition to high quality tape-out.

Description

As a Physical Design lead you will be in charge of all phases of physical design of high performance IP design from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: Create full chip floorplan including partitioning, power domains and power grid planning and design. Develop and validate high performance low power clock network guidelines. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run Physical design verification flow at chip/block level. Participate in establishing CAD and physical design methodologies for correct by construction designs. Assist in flow development for chip integration.

Minimum Qualifications

The ideal candidate will have 7+ years of Physical Design experience on high performance, low power SOC
Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, Floorplaning, and Place & Route
Experience in developing and implementing Powergrid and Clock specifications
Solid Understanding of all aspects of Physical construction , Integration and Physical Verification
Working Knowledge of Basic SoC Architecture and HDL languages like verilog to be able to work with logic design team on timing fixes
Power user of industry standard Physical Design & Synthesis tools
Solid Understanding of scripting languages such as Perl/Tcl
Working knowledge of Extraction and STA methodology and tools
Good understanding of Physical Design Verification methodology to debug LVS/DRC issues at chip/block level
BS.c / MS.c in EE or equivalent experience in Electrical Engineering

Preferred Qualifications

Strong communication skills are a must, as the candidate will interface with a lot of different groups within the company
Ability to work well in a team and be productive under tight schedule

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