Senior ASIC design engineer

Company Description

NeoLogic was founded to address the increasing workloads of video, artificial intelligence, machine learning, data analytics, and more in the cloud and at the edge. We are a developer of unique, patent-pending, technology (Quasi-CMOS) that cuts down the transistor count of circuits by a factor of up to 3x at any technology node. Most of today’s processing infrastructure relies on a 40-year-old processor technology. To address the challenges of modern computing, NeoLogic has developed the industry’s first Quasi-CMOS design technology from the ground up. Our designs are scalable as well as portable to any technology node and deliver power efficiency at a small floor plan combined with high performance.

With an experienced technical team and a superior VLSI design technology, NeoLogic is honed in on innovating VLSI design and powering the next-generation processors past the CMOS era. By building an ecosystem and strong partnerships, NeoLogic introduces a new paradigm of microprocessor design across multiple verticals where reduced power consumption and area, as well as enhanced yield and reliability, can translate into hundreds of millions of dollars in profits and savings for customers.

Role Description

We are looking for a full-time, on-site, senior digital logic engineer, who will be responsible for arithmetic blocks architecture, design, testing and implementation. This role requires strong collaboration with multidisciplinary teams to develop the most efficient solutions.

Qualifications

• Bachelor's or Master's degree in Computer Science, Electrical Engineering, or related field
• Experience in micro-architecture and design of arithmetic blocks (adders, multipliers, etc.)
• Hands-on programming experience in Verilog and Python
• Ability to analyze complex technical requirements
• Excellent problem-solving and decision-making skills
• Experience in Logic Synthesis using DesignWare or ChipWare is a big plus
• Experience in processor technology is a plus