Physical Design Sub Full Chip / IP Layout Lead

Mobileye EyeC VLSI team - a group designing the chips for RADAR systems from advanced ADAS to Full Autonomous Driving.Our Physical Design group is working in a Startup like environment with respect to technical expertise, execution & responsibility .Each Physical Design engineer has an E2E responsibility from definition, execution & full signoffs, working closely with design & architecture teams for constraints development, design review & RTL modifications to achieve convergesWe’re looking for a Physical Design Expert to join the growing Technology Methodology & Execution team, that is responsible for developing both Technology Methodologies & Flows for all products and processes and the execution of complex Subsystems/IPs for our next generation Imagining Radar SoC from definition to Tape-Out.What will your job look like:Leading Subsystem/IP Layout activities for complex Sub Full Chip with several levels of hierarchies.Floorplanning, top-down deliveries & bottom up rollup , Sub FC/ IP level integration & verification.Signoff on all physical design domains PV, IR/EM, LEC, LP Verification.Physical Verification expert, building, maintaining and enhancing the flow for new technologies, improving reliability & convergence ToT.Servings as a technical expert while mentoring and guiding team members,Hands-on physical design block owner from RTL to GDS , an option.All you need is:BSc/MSc in Electrical Engineering/Computer Science.8+ years of experience in VLSI backend (RTL2GDS).5+ years of experience in IP or Full Chip Integration & Physical Verification on complex IPs or SoCs.Expert knowledge in P&R & signoff methodologies.Experience in technically leading complex backend activities, preferably of complete SoC's.Expert knowledge of the entire backend design flow from RTL to TO (Synthesis, FP, PnR, CTS, STA, LP, EM/IR, Chip Integration).Team player with excellent communication skills, customer orientation, and a “can-do” attitude