Sr Principal Design Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence's new Tensilica SW group is looking for R&D FW/SW engineer for new Core technology projects.

The R&D engineer mission will be involved in researching and developing FW, Toolchain, BSP/PSP development for MCU's/CPU's, and Linux distro builds. All work will be cooperated and synchronized with other team members.

Requirements:

Bachelor's degree or higher in EE/Computer Science
Minimum 8-10 years of recent experience with Embedded Linux
Experience in C/C++ and ASM
Experience with Embedded Linux and RTOS's
Experience with GNU/LLVM toolchains
Familiar with developing in a Linux and Windows environment.
High English skills (must): listening, speaking, reading

Advantage:

Previous experience in building distros to embedded linux platforms.
Building Toolchain and integrating them to BareMetal runtime and OS runtime
Experience with Yocto (OpenEmbedded)
Previous experience in working closely with HW-MCUs/CPUs
Previous experience in toolchain development: LLVM with clang FE and/or GNU Toolchains
Previous experience with QEMU emulator
Experience with GNU LD (linker scripts), Binutils, GDB, GCC
Experience in JAVA, Python, C++
Experience with RISCV ISA
Experience with RISC-V OpenSBI
Experience with LAVA framework

Skills:

Working in a team alongside working alone
Open-minded to "brainstorming."
Share knowledge and be willing to work together
A self-learner/autodidact with a research approach
System viewability to spot in advance long-term issues that are hard to see in the short-term
Strong, active listening skills can help in asking thoughtful and probing questions to determine the most suitable/robust solutions.
Highly motivated with the ability to work collaboratively in a fast-paced team environment.

We’re doing work that matters. Help us solve what others can’t.