Wafer-Scale System: Computation (LLM) and Communication (NoC) Co-Design

Required Wafer-Scale System: Computation (LLM) and Communication (NoC) Co-DesignIn this job opening, we are seeking a highly motivated and visionary researcher to join our team focused on chiplet-based computing systems. This role involves research and development in chiplet-based architectures, aiming to overcome performance and scalability limits of traditional compute platforms.Responsibilities:Conduct cutting-edge research on the co-design of communication and computation for wafer-scale systems. On the communication side, the work focuses on architecting Networks-on-Chip, providing scalable, high-bandwidth, and ultra-low-latency interconnects that efficiently span multiple dies and support fine-grained data movement. On the computation side, the research emphasizes optimizing and mapping training and inference workloads to fully exploit wafer-scale resources, improving performance, scalability, and energy efficiency through intelligent task placement and scheduling.Investigatדרישות:Master in Electrical Engineering, Computer Engineering, Computer Science, or a closely related field.Background in interconnection networks and computer architecture is a must.Demonstrated research expertise in one or both of the following areas:Network-on-Chip (NoC) architecture, including routing, flow control, topologies, and performance modelingLLM parallel execution and co-design, including workload decomposition, communication-computation overlap, and mapping to high-performance interconnectsExcellent analytical, problem-solving, and system-level thinking skills.Excellent programming skills with hands-on experience in simulator modeling, development and simulator-based evaluation.Strong verbal and written communication skills, and the ability to work both independently and collaboratively in a cross-disciplinary team. המשרה מיועדת לנשים ולגברים כאחד.