Physical Design Engineer, SoC Static Timing Analysis

Required Physical Design Engineer, SoC Static Timing Analysis
About the job
In this role, youll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers our most demanding AI/ML applications. Youll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our direct-to-consumer products. In this role, you will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering exceptional

דרישות:

Minimum qualifications:
Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience.
8 years of Physical Design experience including 5 years of experience with Static Timing Analysis (STA), including sign-off corner definitions, process margining, interface timing constraints, timing convergence, and setting frequency goals with technology scaling.
Experience in constraints development for subsystems or full System-on-Chip (SoC) architectures.
Preferred qualifications:
Proficiency with scripting languages commonly used in hardware automation (e.g., Tcl, Python, or Perl).
Deep familiarity with ASIC physical design flows and methodologies, including synthesis, place and route (P&R), formal verification, and clock domain crossing (CDC).
Solid fundamental knowledge of semiconductor device physics and transistor characteristics. המשרה מיועדת לנשים ולגברים כאחד.