Package Layout Design Engineer - AI Silicon Packaging

We are seeking a Package Layout Design Engineer to join our hardware team and contribute to the physical design of advanced IC packages for next-generation machine learning and data center ASICs.
In this role, you will execute package layout tasks from floor planning through tape out and manufacturing release, working closely with senior engineers, SI/PI, thermal, and manufacturing teams to deliver production-ready designs that meet performance, density, and reliability targets.

Key job responsibilities
- Execute package layout tasks across the design cycle: die floor planning, bump/pad assignment, RDL routing, substrate design, verification, and tape out release.
- Implement physical designs for advanced packaging architectures including 2.5D interposer, 3D-IC, fan-out wafer-level packaging, and silicon bridge technologies (e.g., CoWoS, EMIB, or similar).
- Support package floorplan development considering die placement, bump maps, power/ground distribution, signal escape routing, a

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Basic Qualifications
- Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills.
- Experience verifying at multiple levels of logic from IP blocks to SoCs to full system testing.
- 5+ years of experience in IC package layout and physical design.
- Experience executing package designs from concept through tape out for multi-layer organic substrates or silicon interposers.
- Hands-on experience with package layout tools such as Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, or equivalent.
- Understanding of advanced packaging technologies: 2.5D/3D-IC, fan-out WLP, RDL, TSV, microbump, or silicon bridge interconnects.
- Working knowledge of package design rules, DFM constraints, and physical verification methodologies (DRC, connectivity checks).
- Experience with bump map and ball map definition, escape routing strategies, and power/ground plane design.
- Good communication skills with the ability to work effe