Senior ASIC Design Infrastructure & Methodologies engineer

We're looking for a strong engineer who is passionate about creating design flows and automation flows that enhance both the productivity and quality of our design team. The ideal candidate brings proven expertise in RTL design and front-end methodologies while having good software skills and a drive for improving and automating flows. In this role, you'll collaborate closely with architects, designers, verification engineers, and other cross-functional team members to refine existing design flows and introduce innovative automation solutions that streamline flows and elevate overall design quality.
Key job responsibilities

Core Responsibilities:
- Develop and implement new methodologies and infrastructure to empower design teams to operate efficiently while maintaining high-quality standards.
- Enhance and build design flows to boost the overall productivity of design teams.
- Collaborate with vendors to evaluate and qualify new design tools and updated tool versions.

דרישות:

Basic Qualifications
- 7+ years of ASIC implementation, synthesis, STA and physical design in deep sub-micron nodes (16nm or smaller) experience.
- 7+ years of digital design in communication systems experience.
- 7+ years of full-custom analog or RF layout experience.
- 7+ years of wireless communications systems and implementation experience.
- 8+ years of creating and maintaining automation frameworks for Post-Silicon Flow experience.
- 7+ years of verification in communication systems experience.
- 5+ years of UVM, C, System C, and scripting experience.

Preferred Qualifications
- Master's degree or Ph.D. degree in Electrical Engineering or related field.
- Experience in RTL coding and debug, as well as performance, power, area analysis and trade-offs.
- Experience with modern ASIC/FPGA design and verification tools.
- Experience with SOC bring-up and post-silicon validation. המשרה מיועדת לנשים ולגברים כאחד.