Senior Manager, Analog IP Design

We are seeking an exceptional an exceptional leader to build and lead our next-generation internal Analog IP design team. This is a unique opportunity to create a world-class analog design center from the ground up, developing the critical IP blocks that power all of our custom silicon products, including Graviton (server CPUs) and Nitro (networking/security accelerators).

Key job responsibilities
Build the team: Recruit, hire, and develop a world-class analog/mixed-signal design team from the ground up. Define the org structure, roles, and growth path.

Define the IP strategy: Own the analog IP roadmap across all Annapurna Labs products. Evaluate build vs. buy decisions and drive internal capability development.

Drive execution: Lead the full design cycle from architecture through silicon validation - spec, schematic, layout, simulation, tapeout, and bring-up.

Collaborate cross-functionally: Partner with SoC architecture, digital design, physical design, DFT, packaging, and system

דרישות:

Basic Qualifications
- B.Sc. in Electrical Engineering.
- 15+ years of hands-on analog/mixed-signal design experience in advanced CMOS nodes (7nm and below).
- 5+ years of proven engineering management experience, including building and scaling teams.
- Deep expertise in one or more: high-speed SerDes/PHY, PLL/DLL, data converters, LDOs/power management, or I/O interfaces.
- Track record of successful tapeouts and silicon bring-up in volume production.
- Experience with design methodologies for IP portability and reuse across multiple process nodes.
- Strong understanding of semiconductor physics, device modeling, and process technology.

Preferred Qualifications
- Experience with die-to-die interfaces (UCIe, HBI) or advanced packaging (2.5D/3D).
- Experience with integrated voltage regulators (IVR) for high-performance compute.
- Experience leading analog IP development in a hyperscaler or large semiconductor company.
- Familiarity with GPIO design for multi-standard (LPDDR, PCIe, CX