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מעל 80,000 משרות • 4,000 חדשות ביום
חינם. בלי פרסומות. בלי אותיות קטנות.

Senior Physical Design Verification Layout Engineer

Nvidia

מספר מקומות

Senior Physical Design Verification Layout Engineer

Nvidia

מספר מקומות
מלאה
25,000-40,000 ₪ (הערכה מבוססת AI)
זוהי הערכת טווח שכר מבוססת AI ולא פרסום של המעסיק

We are looking for best-in-class Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in designing our groundbreaking and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
You will be responsible for chip floorplan and pin placement, ensuring integration within our innovative builds.
We expect you to run, debug, and approve Physical Verification flows across multiple projects, ensuring strict adherence to our high standards.
You will perform physical layout implementation, planning and optimization, contributing to the development of our groundbreaking chips.

דרישות:

What we need to see:
B.SC./ M.SC. in Electrical Engineering
You should have at least 5+ years of hands-on layout experience, demonstrating your proven expertise.
A strong background in Physical Verification methodology, including ERC, LVS and DRC, is necessary.
In-depth knowledge of advanced silicon process technologies.
Familiarity with physical build EDA tools, including Synopsys and Cadence.
A great teammate who thrives in a collaborative environment.
AI tools orientation or alternatively a desire to learn.
Ways to stand out from the crowd:
Experience in Linux environments.
TCL, Python, shell scripting abilities.
Experience with data collection and analysis
Understanding of the chip and die verification process. המשרה מיועדת לנשים ולגברים כאחד.