senior vlsi cdc engineer

the complexity of the chip has greatly increased over the years. we are now packing tens of billions of transistors in a chip to meet the growing computing demand in a footprint that is responsible to our environment. the company system -on-chip ( SOC ) group is looking for a top asic engineer with a curiosity about SOC design automation, rtl integration, chip build and assembly, and padring design and verification. you should have real passion for methodologies and automation solutions that enable SOC creation in the most optimized way.
in this position, you will get the opportunity to build complex networking chips and interact directly with unit-level asic, physical design, cad, package design, software, dft and other teams. 
what you'll be doing:
lead the end-to-end execution, tracking, and convergence of chip-level cdc and rdc for complex socs across all ips and partitions.
plan and orchestrate cdc/rdc signoff: define methodology, scopes, run plans, constraints, and acceptan

דרישות:

what we need to see:
b.sc./ m.sc. in electrical engineering/computer engineering.
7+ years of actual design experience in chip design
strong rtl proficiency in systemverilog for reading/debugging designs and implementing cdc/rdc-safe structures.
experience with constraints and timing intent (sdc) and their interaction with cdc/rdc.
hands-on expertise with industry cdc/rdc tools (e.g., spyglass, questa cdc, real intent) and lint/formal where relevant.
proficiency in at least one scripting languages like Python, bash, PERL, tcl.
great teammate.
way to stand out from the crowd:
passion for quality. experience with delivery to physical design and other customers
our company has some of the most forward-thinking people in the world working for us. are you a creative and autonomous engineer who loves a challenge? are you ready to become the engineer you always wanted to be? come and be part of the best physical design team in the industry! המשרה מיועדת לנשים ולגברים כאחד.