senior sta engineer, sub-chip

our team in israel is looking for a dedicated chiplet sta owner to join us in defining the next era of ai's networking. this is an outstanding opportunity to work with innovative technology and collaborate with some of the most experienced minds in the industry. if you are ambitious, passionate about flawless design, and eager to make a lasting impact, this role is perfect for you!
what you'll be doing:
perform advanced static timing analysis (sta) at chiplet and fc level.
running prime time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
identify convergence risks and work closely with physical design, rtl and dft teams, ensuring convergence throughout various project stages.
responsible for a full timing closer and quality approval from pre-layout sta model through signoff.

דרישות:

what we need to see:
b.sc./ m.sc. in electrical engineering.
at least 5+ years of hands-on sta experience.
experience in prime time and signoff methodologies.
excellent leadership capabilities.
ways to stand out from the crowd:
knowledge in physical design flows and methodologies (synthesis, pnr, dft designs).
trong background of prime time tool.
great teammate. המשרה מיועדת לנשים ולגברים כאחד.