senior dpu performance Validation engineer

we are hiring a skilled senior dpu performance  Validation engineer for our dpu product lines. this includes chip architecture performance characterization, debug, and validation across single-die and multi-die systems. working in the network silicon engineering group, you will be responsible for debugging, analyzing, and validating performance and functional behavior of current and future silicon devices. you will collaborate with chip design, verification, fw, and architecture teams to ensure successful product development with bold product cycles. the qualified candidate should be comfortable working in simulation and emulation environments, with strong skills in rtl-level debug, waveform analysis, and  system -level performance root cause analysis.
what you will be doing:
learn and analyze  system -level operation of dpus
debug and root-cause performance issues in pre-silicon environments, across rtl, waveform traces, and multi-die  system simulations.
collaborate closely with

דרישות:

b.sc. in electrical engineering, computer engineering, or equivalent
5+ years of experience in asic development/validation.
strong background in asic debug, including reading rtl, analyzing waveforms, and root-causing functional or performance issues.
hands-on experience with performance validation and analysis at the  system level (die-level or multi-die systems).
proficiency with  Python and  C /  C ++ in a  Linux environment.
excellent interpersonal skills and ability to work optimally as part of a multi-functional team.
ways to stand out from the crowd:
shown expertise in performance modeling, traffic generation, or architecture studies.
experience with modern interconnects and protocols (e.g., pcie, ethernet, chi).
familiarity with emulation platforms (e.g., palladium, veloce, fpga prototyping).
passion for experimental work,  data -driven validation, and creative problem solving. המשרה מיועדת לנשים ולגברים כאחד.