Design Technology Co-Optimization Engineer

In this role, you will conduct Place and Route experiments and sensitivity analyses to influence standard cell library architecture, metal stack definitions, and design rules. You will collaborate with Foundry, IP, and Architecture teams to identify Power, Performance, and Area (PPA) bottlenecks and drive System Technology Co-Optimization (STCO) initiatives.
Your work will involve performing high-fidelity physical implementation sweeps, analyzing the impact of scaling boosters, and developing automated methodologies to quantify PPA gains. By navigating the trade-offs between process complexity and design performance, you will ensure our companys hardware achieves efficiency and power density.
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Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
2 years of experience in Physical Design (RTL-to-GDS) or Technology Development, focusing on advanced nodes (e.g., 7nm, 5nm, or below).
Experience with industry-standard Place and Route (P&R) tools and Static Timing Analysis (STA) tools.
Experience in CMOS device physics, FinFET/nanosheet architectures, and the impact of layout parasitics on PPA.
Experience in scripting and automation using Tcl and Python (or Perl) to manage design sweeps and data extraction.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience in Design Technology Co-Optimization (DTCO), including standard cell library characterization, metal stack optimization, and evaluation of scaling boosters (e.g., backside power delivery).
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