Physical Design Engineer, Full Chip Layout

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of our company's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of our company platforms, we make our company's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.
Responsibilities
Develop and optimize the overall layout of the chip, including partitioning, macro and IP placement, and pin placement

דרישות:

Minimum qualifications:
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience with physical design flows and methodologies (RTL2GDS).
Experience with semiconductor process technologies (deep submicron, advanced nodes like 5nm and below), and device physics (MOSFET/FINFET).
Experience with design for testability (DFT) and low-power design methodologies.
Experience with UPF (Unified Power Format) and its application in physical design.
Preferred qualifications:
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with scripting languages such as Perl, Python, or Tcl.
Excellent analysis skills, with the ability to understand, debug, and resolve issues in the design flow. המשרה מיועדת לנשים ולגברים כאחד.