Compiler Circuit Designer

Summary

Posted: Nov 19, 2024

Role Number:200579584

Do you want to utilize your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule? Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you’ll take imaginative and revolutionary ideas and determine how to turn them into reality. You and your team will apply engineering fundamentals and start from scratch if needed, bringing visionary ideas to the real world. Your efforts will be groundbreaking, often literally. Join us, and you’ll help design the tools that allow us to bring customers experiences they’ve never before imagined. You will be part of an exciting silicon design group that is responsible for designing state-of-the-art ASICs. We have an extraordinary opportunity for Compiler Circuit Design Engineers. This is a highly visible role at the heart of a processor design effort, making a critical impact delivering products to market quickly.

Description

Imagine yourself at the center of our hardware development effort. In this role, on memory compiler, you will collaborate with compiler vendors and design teams. You will have the opportunity to integrate and come-up with new ideas, as well as work with a team of talented engineers. You will work closely with compiler development and deployment to impact PPA of the end products. As a Compiler Circuit Design engineer for digital design team, you will perform the following: * Drive the development of SRAM, register files and latch arrays to enable high performance and low power design * Have as comprehensive understanding of IC compilers that are available globally * Lead the SRAM compiler IP requirements to Vendors and the internal IP teams * Understand the complete spectrum of design flow, DFT and testing aspects of the compiler IPs * Work with logic/architecture team to capture specifications of SRAM/Reg files/Latch arrays and drive the implementation.

Minimum Qualifications

• We are looking for applicants with expertise in developing high-performance low power circuit design and SRAM and register file arrays
• Solid knowledge of industry standard circuit simulation and design tools, top-level integration tools.
• Ability to conduct and review experiments during silicon debug, gather & analyze data
• Experience in leading cross-functional teams by technical expertise and to present complex technical topics to a multi-level audience

Preferred Qualifications

Proven understanding of device physics and process.
Drive multi-functional team for failure analysis, corrective action implementation plan, and yield bridge to a successful ramp & mass production.
Exposure to transistor-level static timing and noise flows
Ability to drive automation for rapid and dynamic design needs.