SoC Design Engineer

Wiliot was founded by the team that invented one of the technologies at the heart of 5G. Their next vision was to develop an IoT sticker, a computing element that can power itself by harvesting radio frequency energy, bringing connectivity and intelligence to everyday products and packaging, things previously disconnect from the IoT. This revolutionary mixture of cloud and semiconductor technology is being used by some of the world’s largest consumer, retail, food and pharmaceutical companies to change the way we make, distribute, sell, use and recycle products.

Our investors include Softbank, Amazon, Alibaba, Verizon, NTT DoCoMo, Qualcomm and PepsiCo.

We're seeking a driven and experienced Digital Designer to join our dynamic team and contribute to our cutting-edge battery-less Ultra low-power System-on-Chip (SoC) project. If you have a minimum of 3 years of hands-on experience in SOC design and a strong desire to innovate, we want to hear from you!

Requirements:

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Minimum 3 years of experience in SOC design.
Strong understanding of digital design principles and CMOS technology.
Proficiency in Verilog or SystemVerilog for design.
Experience with industry-standard EDA tools (e.g., Synopsys, Cadence, Mentor Graphics).
Knowledge of low-power design techniques (e.g., clock gating, power gating, multi-voltage domains, UPF).
Experience with timing analysis and closure.
Excellent problem-solving and debugging skills.
Strong communication and teamwork abilities.
Advantages: Experience with RISC-V based SoC.
Advantages: knowledge of using cdc technics.
Advantages: knowledge of SV-UVM, UPF technics, CPU (RISC-V), and FW code.
Advantages: knowledge of MCU SoC Arch. , Analog ICs, Mix-signals design and Lab equipment.

#LI-Hybrid

Responsibilities:

Design and implement complex digital circuits for ultra low-power SoC.
Participate in all phases of SoC design, from specification to coding, debug and tape-out.
Perform RTL design, synthesis, and timing analysis.
Optimize designs for power, performance, and area (PPA).
Collaborate with cross-functional teams, including architecture, System, Software, Analog, verification, and physical design engineers.
Contribute to the development of design methodologies and best practices.
Debug and resolve design issues.
Support Lab bring ups, debug and other activities